This application claims the priority benefit of Taiwan application serial no. 89125862, filed Dec. 5, 2000.
1. Field of Invention
The present invention relates to an apparatus and a method for executing processor instructions. More particularly, the present invention relates to an apparatus for executing a block data transfer instruction inside a processor.
2. Description of Related Art
Processor is an indispensable apparatus in many electronic products. For example, every computer must have at least one central processing unit and various controllers need to have one or more special function processors. As increasingly powerful electronic equipment is developed, the role played by processors is increasingly important.
To attain a higher level of performance, one obvious solution is to shorten the clock cycle or in other words, increase the operating frequency. Another way of increasing performance is to execute a multiple of instructions simultaneously in each clock cycle.
Among the list of instructions provided by a processor, there is one special purpose instruction for processing the data in a whole block of registers. For example, data can be read from or written into a whole block of registers with one instruction. Using a 16-register block as an example, to execute the instruction, a processor has to perform identical operations for each of the registers in the list, operations such as the transfer of data. This mode of operation is not wasteful when all 16 registers contain transferable data because the processor executing time is fully utilized. However, the number of registers that actually has to be dealt with is smaller than 16, or as low as 1, the rule of dealing with all 16 registers is quite wasteful and may lower processing efficiency. On the other hand, using the conventional technique, at least 16 program codes are necessary to implement the transferring operation, it means that a longer size of program codes is necessary. It will waste too many program codes to implement the instruction.
Accordingly, one object of the present invention is to provide an apparatus and method for executing block data transfer instruction inside a processor. The apparatus is capable of finding out the registers and their corresponding addresses that must be processed from the decode information of a register list. By processing the data in the specified registers only, program code as well as the processor executing cycles can be reduced. Hence, performance of the processor can be improved considerably.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an apparatus for executing block data transfer instruction inside a processor. The apparatus is able to receive a decode information having at least N bits. The apparatus includes an adder, a counter, a register identification number generator, a memory unit and a register list. The adder receives the N-bit decode information and then adds the bit values of the N-bit decode information together to obtain an initial count value. The counter receives the initial count value. The initial count value is decrement by one on each encounter. A count control signal is then issued by the counter. According to the count control signal, the register identification number generator produces a plurality of register identification numbers (IDs) that are equivalent in number to the initial count value. These register identification numbers correspond to the positions in the N-bit decode information that has a value of xe2x80x981xe2x80x99. The memory unit is a place for holding data. The register list includes a plurality of registers. The register list receives the register identification (ID) numbers. According to the register identification numbers, data are free to transfer between the memory unit and a register corresponding to a register identification number.
The block data transfer apparatus further includes an address calculator. The address calculator generates an address signal according to the decode information. The address signal is sent to the memory unit. Data is transferred between the register that corresponds to a particular register ID number and the memory unit that corresponds to a particular address signal.
The register ID number generator of the block data transfer apparatus further includes N logic units for producing a number of register ID numbers equivalent to the initial count value. The counter subtracts one from the initial count value until the value zero is reached. The N logic units generate corresponding register ID numbers according to the positions in the N-bit decode information having a bit value of xe2x80x981xe2x80x99.
This invention also provides a method of executing block data transfer instruction inside a processor after receiving an N-bit decode information. The method includes adding the N bits in the N-bit decode information together to form an initial count value, and generating a plurality of register identification (ID) numbers equivalent in number to the initial count value. The register ID numbers correspond to the positions in the N-bit decode information that has a bit value xe2x80x981xe2x80x99. According to the register ID number, a link is created between the plurality of registers corresponding to the register ID numbers and a memory unit so that the memory unit and the registers are free to exchange stored data.
In the block data transfer method, the step for generating the register ID numbers further includes subtracting one from the initial count value after each encounter. The counting operation decrements the initial count value by one until a value zero is obtained. After each decrement operation, a register ID number is generated according to whether the position in the N-bit decode information has a bit value of xe2x80x981xe2x80x99 or not.
The block data transfer method further includes generating an address signal according to the decode information. Hence, data is free to exchange between a register corresponding to a particular register ID number and a memory location corresponding to the address signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.